The Xbox 360 CPU has 3 x VMX units. And there are "
128 registers per hardware thread" (see
Xbox 360 Fact Sheet).
I recall that SPE implementation in Cell were originally stated to have VMX ISA (am I correct?), but Altivec was in fact too limited with 32 registers. So IBM went further and designed the SPE wider, with 128 registers.
Is there any difference between "128 registers" and "128 registers per hardware thread"? How much registers per hardware thread does the G5 has?