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Originally Posted by tokamac
The Xbox 360 CPU has 3 x VMX units. And there are " 128 registers per hardware thread" (see Xbox 360 Fact Sheet).
I recall that SPE implementation in Cell were originally stated to have VMX ISA (am I correct?), but Altivec was in fact too limited with 32 registers. So IBM went further and designed the SPE wider, with 128 registers.
Is there any difference between "128 registers" and "128 registers per hardware thread"? How much registers per hardware thread does the G5 has? |
In both cases programs have 128 registers available to use (actually VMX128 also has the normal PowerPC integer and float registers -- 32 of each). The "per hardware thread" thing means that the execution units of the core are shared between two threads... if each of those threads could fully use the processor then doing that would cut their speeds in half. Since most threads actually spending a lot of their time waiting, however, their resources aren't always busy anyhow so sharing them doesn't cost anything much of the time. In practice this means that you have two hardware threads running slower than one would, but faster than half the speed of just one.
The SPE, on the other hand, is designed from the ground up to have 128 vector registers and it has local very high speed memory of its very own to play in (plus a DMA controller to bring things in and out while the SPE core is busy working). The SPE is also smaller, which is how Sony/IBM has managed to fit 1 PPE + 8 SPEs onto a single chip, compared to Microsoft/IBM's 3 enhanced PPEs (or something so similar as to be equivalent). That's 9 cores to 3, and now it looks like they'll be at the same clock rate.