It's likely that the Cell and Waternoose (Trinity?) have similar cores, with a long pipeline but very limited logic depth per stage. Overall, it has lower leakage and runs fast, but performs poorly compared with the Power series cores. Yet it is a tradeoff. The design allows IBM to add more cores to the chip. At this point, nobody may know where the future of CPU design is headed for sure. Once Apple has all the chips to try out, the design that performs best will likely win. Here is a quote from David Wang's article:
Jerry
" . . . the paper published in ISSCC 2000 described a processor that supported the complete POWERPC instruction set and operated at 1 GHz on a 0.25µm process technology. The microarchitecture of the research processor was disclosed in some detail in the ISSCC 2000 paper. However, that processor was a single issue processor whose design goal was to reach high operating frequency by limiting pipestage delay to 13 FO4, and power consumption limitations were not considered. For the PPE, several major changes in the design goal dictated changes in the microarchitecture from the research processor disclosed at ISSCC in 2000. Firstly, to further increase frequency, the per stage circuit delay design target was lowered from 13 FO4 to 11 FO4. Secondly, limiting power consumption and minimize leakage current were added as high priority design goals for the PPE. Collectively, these changes limited the per stage logic depth, and the pipeline was lengthened as a result. The addition of SMT and the two issue design goal completed the metamorphosis of the research processor to the PPE. The result is a processing core that operates at a high frequency with relatively low power consumption, and perhaps relatively poorer scalar performance compared to the beefy POWER5 processor core."
http://www.realworldtech.com/page.cf...WT021005084318