[LudwigVan]

I see ThinkSecret is hot on the case now too.

[hmurchison]

Originally Posted by LudwigVan I see ThinkSecret is hot on the case now too.

Methinks perhaps Morpheus and Thinksecret's "sources" are one in the same.

Bring on the Quads!!

[Eugene]

Originally Posted by hmurchison Bring on the Quads!!

A far premature specification, I think. 154mm^2 90nm core x 2 = you're going to need a bigger boat.

[DMBand0026]

Originally Posted by LudwigVan I see ThinkSecret is hot on the case now too.

Haha. Most of that article made sense to me. You guys might as well be speaking Chinese, cause I don't understand 93% of this thread

This is exciting though, I hope IBM can push the dual core stuff out the door before AMD and Intel.

[DrGruv]

What happened to the 980 Q3 of 2004?

I was expecting the 980 based on the power 5 in jan. 05.

PERHAPS, an IDEA...

NEW powerpc980 for the pro market?

New 970 chip for laptops and imac - throttled down to a lower power for powerbooks and imacs YET still having peformance from the dual core?

(just a thought) (no flames) What do you think? Plausible?

-mike

[hmurchison]

Originally Posted by Eugene A far premature specification, I think. 154mm^2 90nm core x 2 = you're going to need a bigger boat.

Premature Specification indeed

However in light of Morpheus' posted pdf about heat dissipation it seems that the Dual 2.5 PM is over engineered going with liquid cooling. I believe the first G5s where about 120mm squared per proc. So the duals used 240mm of total space. Would it really be that hard to shoe horn in another 68mm total and keep them cool? Perhaps but with improved Powertune and SOI not to mention liquid cooling the idea doesn't seem as far fetched after first reflection.

[onlooker.org]

just saying hi! What the heck? Was this appleinsider.org once?

I like the new name better. No legacy BS.

[Morpheus]

No comment. :smokey:

May all your dreams be good dreams,

Morpheus
God of Dreams, Ruler of the Shadowlands

[iMeowbot]

Originally Posted by iMeowbot Higher clocking might not be so far-fetched. It *is* two cores, and they're implementing PowerTune and independent caches, which hints at (but doesn't dictate) independent clocks and asynchronous glue. *If* they've gone partially async, propagation delays hold a lot less sway over what the clocked sections do. It also makes overall throughput much, much harder to guess at.

...and in the ThinkSecret version of the story, it does use the elastic bus from POWER4. This deals with memory clock skew by using handshaking, while traditional interfaces just clock everything down to the worst case delay. Not just better overall performance here, but the longer wire lengths it allows will simplify cooling problems and open up some possibilities for external interfaces. Not quite the same as async, but very similar benefits. Neat.

[Moogs]

I don't know about you guys but Dual-processor, Dual-core G5 would be the first computer Apple has released in a long time, that would actually make me want to sell an already kick-ass machine (Dual 2Gig G5) to get a newer model. That would likely be a quantum jump in performance, especially with the new stuff going into Tiger (AFAICT).

I aspire to the day when turning on my Mac will be as responsive as turning on my television. 5 second boot time, anyone?

[CoreMac]

Originally Posted by Moogs I aspire to the day when turning on my Mac will be as responsive as turning on my television. 5 second boot time, anyone?

Sorry, but you'll need to sell that Dual Dual G5 and buy a Dual Quad 980 for that.

[Spart]

A question to those who might know:

Given a current dual 2.5 GHz G5 machine with one bus per processor vs. a dual core, single chip 2.5 GHz G5 with one bus per dual core processor, would the non-dual-core version be faster at some tasks because of the twin elastic busses? Besides differences caused by larger caches and whatnot...

[hmurchison]

Originally Posted by Spart A question to those who might know: Given a current dual 2.5 GHz G5 machine with one bus per processor vs. a dual core, single chip 2.5 GHz G5 with one bus per dual core processor, would the non-dual-core version be faster at some tasks because of the twin elastic busses? Besides differences caused by larger caches and whatnot...

I don't think the Twin FSBs would make much of a difference. You still have Dual Channel PC3200 memory as the "real" bottleneck. 6.4GBps is nice but the 1250Mhz bus alone can handle 5GBps up/down. So the 1250 FSB only becomes a limitation when we hit more than 10GBps memory throughput which would be DDR2 667 in Dual Channel config (PC 5300)

[Powerdoc]

Originally Posted by hmurchison I don't think the Twin FSBs would make much of a difference. You still have Dual Channel PC3200 memory as the "real" bottleneck. 6.4GBps is nice but the 1250Mhz bus alone can handle 5GBps up/down. So the 1250 FSB only becomes a limitation when we hit more than 10GBps memory throughput which would be DDR2 667 in Dual Channel config (PC 5300)

Exactly the dual FSB make only sense if you have two separates chips : there is no penalty hit for sharing the same bus. A dual core chip has only one memory*bus, but the two core will be interconnect at full clock speed. Futhermore, the latency between the two cores, will be much smaller than the one of two separate chips.

It's nearly*sure that a 1,25 ghz bus, won't do much difference against a simple 1 ghz bus, with dual channel PC memory and it's 6,4 GB/sec. Apple did go for the 1,25 ghz bus with the 2,5 ghz bus, because there is a limited choice of ratio between the chip and the bus : 1/2, 1/3 (and smaller), and the use of 1/3 with a 2,5 GB/sec chip will induce a performant penalty. At 3 ghz the bus is clocked at 1 ghz, something sufficiant for exploiting at 100 % the memory bandwitch of the mobo.
I am ready to bet, that if Apple shipped a 3 ghz G5 on the current design (PPC 970 fx) , he will use the 1 ghz bus, and not the 1,5 ghz one.

[staph]

You'll all be glad to know that this just got us referenced at The Register

[Barto]

Urgh. Getting referenced by TheReg for having inside information is like getting referenced by John Howard (or George Bush, or Tony Blair) for having Iraq intelligence.

[alcimedes]

yeah, but the BOFH makes up for any wrong doing.

[Powerdoc]

Some people wonder why IBM won't produce directly an multithreaded bi core PPC 970 à la power 5.
I think that the main reason is the size. The core of the PPC 970 mp is certainly larger than the PPC 970 due to the deeper pipelining (and the more a chip is pipelined, the more transistors it recquieres). Adding multithreading will recquieres 25 % more transistors. At 90 nm the heat issue could become critical.
That's why multithreaded may be a feature that will appear when IBM switch for 65 nm process.

[hmurchison]

Originally Posted by Powerdoc Some people wonder why IBM won't produce directly an multithreaded bi core PPC 970 à la power 5. I think that the main reason is the size. The core of the PPC 970 mp is certainly larger than the PPC 970 due to the deeper pipelining (and the more a chip is pipelined, the more transistors it recquieres). Adding multithreading will recquieres 25 % more transistors. At 90 nm the heat issue could become critical. That's why multithreaded may be a feature that will appear when IBM switch for 65 nm process.

Powerdoc that's what I'm thinking. I also think Apple will keep the ondie memory controller functions as well for the mythical 980. You have to figure, just doing rough estimates, that the inclusion of SMT, OMC and dual-cores in a POWER5 derivative would be 170mm+ die. Moving to 65nm should drop that back to 80-100mm yet we get all the "goodies".

[ATS]

eWeek has an article about the new dual-core PPC, which it says will be "available for testing purposes later this summer."

[jl51]

Originally Posted by oldmacfan Why am I only gettting 3 pages of the PDF?

Where and how to get the pdf

[gsxrboy]

Almost a whole month and no new gossip?

[Morpheus]

Originally Posted by gsxrboy Almost a whole month and no new gossip?

970GX

Morpheus

[DrGruv]

Originally Posted by Morpheus 970GX Morpheus

Boy's got the goods

come on --- spill it!!!!

What is the 970GX?

-mike

[Henriok]

Originally Posted by Morpheus 970GX

Let me guess... "nothing" more that 1 MB L2 cache? Can we expect speed bumps and som other goodies too? I hear that we can expect 970GX in about 6 months time, do you concur?

[jl51]

Originally Posted by Morpheus 970GX

Welcome back Morpheus !

Is the 970GX the son of the 970FX as the 750GX is the son of the 750FX ?

A low power 970GX would be a good chip for embeded computing and laptops.

[DrGruv]

Well?

c'mon man drop the other shoe...

[kscherer]

Originally Posted by Morpheus Fair enough: Antares is a dual core (two processors on single die) follow-on to Altair, using IBM's CMOS SOI10K technology with SOI (Silicon On Insulator) and copper bus with 10 layers of metal. Each core has a 1M L2 cache. L3 cache is not supported. How is this for a start? Morpheus

Sounds to me like someone has been reading all of the news postings. Care to quote from any other articles?

[AirSluf]

XXXXX

[Henriok]

Originally Posted by kscherer Sounds to me like someone has been reading all of the news postings. Care to quote from any other articles?

Please check your dates. I can guarantee you that this thread was the first. Before all the articles.