[iMeowbot]

Originally Posted by sCreeD "Clock Dithering (New feature for 970FX DD3.0, enhanced in 970MP)" Hmm...

That's part of PowerTune. They're using it to ramp between frequencies so that current surges are smoothed over.

[Barto]

Originally Posted by curiousuburb Antares is in the constellation Scorpio Can we get Carol to measure this CPU's Natal Clock cycles and give a horoscope? "Scorpios are flirtatious in their communications with others and network well" = xGrid benefits?

I'm sitting back, waiting for Carol to chase you around with a switch now

[jeannot]

Very interesting, Morpheus..
Can you tell us if this CPU is taped out ?

[Morpheus]

Originally Posted by jeannot Very interesting, Morpheus.. Can you tell us if this CPU is taped out ?

According to the
traditional definition , yes, it has

Morpheus

[Snoopy]

Originally Posted by Powerdoc . . . This dual core G5 will be huge chip,even, bigger than the power4 (even if there is no L3 cache manager, there is two altivec unit : one for each core). . . This G5 MP, will produce lot of heat. It may be possible to see one in a desktop with the 90 nm process, but we will never see them in an I mac or a powerbook, unless they will be fabbed on 65 nm process.

Maybe the water cooled 970FX is just a shakedown cruise for the upcoming 970MP. Apple may want early experience with water cooling in a less demanding implementation. It will be one less new technology for Apple when the G5 Quads are introduced.

[Morpheus]

Main features: (cont)

In order dispatch of up to five operations into distributed issue queue structure
Out of order issue of up to 10 operations into 10 execution pipelines
- Two load or store operations
- Two fixed-point register-register operations
- Two floating-point operations
- One branch operation
- One condition register operation
- One VMX permute operation
- One VMX ALU operation


(tbc)

Morpheus

[Kurt]

What are the yields going to be on this monster? If IBM is having a hard time with the 970fx how are they going to make a chip that is (or almost) twice as big? I would think that it would be definitely for a high end machine.

Morpheus, any idea what speeds they are planning?

[hmurchison]

Originally Posted by Kurt What are the yields going to be on this monster? If IBM is having a hard time with the 970fx how are they going to make a chip that is (or almost) twice as big? I would think that it would be definitely for a high end machine. Morpheus, any idea what speeds they are planning?

The problems IBM faced are likely due to 90nm transitioning and not size. If that is true then IBM and Apple is correct that 970fx CPU are constrained until Oct 2004 then it's reasonable to conclude that IBM fixed the issue prior to the end of summer and is working on ramping production. If indeed the 970MP is tape out this fall then mass production could commence in January/Feb. Anyone know how long the PPC takes from tapeout to mass prod?

[Kurt]

Originally Posted by hmurchison The problems IBM faced are likely due to 90nm transitioning and not size. If that is true then IBM and Apple is correct that 970fx CPU are constrained until Oct 2004 then it's reasonable to conclude that IBM fixed the issue prior to the end of summer and is working on ramping production. If indeed the 970MP is tape out this fall then mass production could commence in January/Feb. Anyone know how long the PPC takes from tapeout to mass prod?

I understand that a lot of the issues were due to a smaller process size but since every transistor has a certain probability of being faulty, the chances to make a good chip definitely increase as the number of transistors decrease. Therefore, a bigger (more transistors) chip is more likely to have a defect. If IBM is already having problem with the process, I would think that yields on dual core chips are going to be lower.

[Morpheus]

Originally Posted by Kurt Morpheus, any idea what speeds they are planning?

Yes.

Morpheus

[Morpheus]

tpbd!

BTW, an interesting IBM Research report on the PM G5.

Morpheus

[709]

Originally Posted by Morpheus Yes.

[DaveGee]

I can vouch for my dear old brother Morpheus he has a direct line with the Oracle don't ya know.

Dave

I can also vouch for Morpheus. He's never given wrong info, to my knowledge.

Another vouch for Morpheus. Just never seen him so forth coming in public however.

[rickag]

Morpheus

You mention CMOS SOI10KE, but nothing about strained silcon. Just curious, the current 970FX reportedly is using a strained silcon process, but as I understand it not SSDOI(strained silcon directly on insulator). Why your omission of strained silcon, is IBM leaving strained silcon tech behind, or is my understanding of this teminology/process badly misconstrued?

[DaveGee]

Good to see you again FLL!

Dave

[Brad]

FWIW, I can concur that the above new members that "vouched" for Morpheus are unique based on their IPs.

[hmurchison]

The info sounds great but what are we to base these newfound numbers on. Should be be comparing each features with the spec sheet for the 970 processors? What we're missing here is the baseline.

[Kurt]

Originally Posted by Morpheus Yes. Morpheus

What is that saying about all those out of work comedians?

Please tell us what the speeds are going to be.

Also, what is the timeframe for a 970fx at 3GHz?

Thanks.

[DaveGee]

Originally Posted by Kurt What is that saying about all those out of work comedians? Please tell us what the speeds are going to be. Also, what is the timeframe for a 970fx at 3GHz? Thanks.

Speeds?!?! You don't know much about CPU design (and neither do I) but I can say: What the speeds are 'on paper' and what they are when they come off the line usually are two totally different things.

Proof is in the pudding!

That being said I'd guestamate they are shooting for 2.5 to 3 GHz and anything else would be a bonus. After all, TWO cores BOTH running at 3GHz would be amazing and the fact is 2.5 would be amazing considering:

970: ~131 mm
970-fx: 96 mm (I think)
970-mp: ~154mm

2 cores each with their own 1 MB L2 cache!! Heck the initial gpul and even the fx only had 512k. I have a feeling the MP is gonna SCREAM even if it **only** clock to 2.5GHz.

I wish someone could invite 'programmer' over here I'd love to hear his input on these specs. I know I know - we shouldn't but...

Dave

[NosferaDrew]

I miss guys like Programmer when we have threads like these.
Interesting stuff nonetheless.

[PhenixReborn]

Originally Posted by rickag Morpheus You mention CMOS SOI10KE, but nothing about strained silcon. Just curious, the current 970FX reportedly is using a strained silcon process, but as I understand it not SSDOI(strained silcon directly on insulator). Why your omission of strained silcon, is IBM leaving strained silcon tech behind, or is my understanding of this teminology/process badly misconstrued?

Not to answer your question, but here's a quick summary of Strained Si:

By stretching the crystalline structure of the silicon, you can do two things.

The first is that you can match it's structure with other materials. This means you might have better luck with SSOI since the Insulator might not have the same crystalline orentation or cell spacing as the Silicon. By straining the silicon, you can come close to matching the insulator structure and thereby bond the two materials together. You have to bond them together to get a decent chip.

The second reason has to do with increasing the distance between the silicon atoms. When you increase the distance, you increase the probability that a mobile electron will move between two atoms without colliding with either of them. In macroworld terms, this means you have less resistance from the silicon which increases processor speed and reduces heat generation.

To quote from a Nanotechnology book large enough to bludgeon you with:

...MOSFETs with strained Si channels...exhibit superior performance. Leading chip manufacturers have decided to adopt strained silicon for high performance CMOS microporcessors

Does that follow with your understanding of Strained Silicon? If you want more, I'll write up the paragraph they give to strained Si. It's rather informative.

[iMeowbot]

Originally Posted by DaveGee 2 cores each with their own 1 MB L2 cache!! Heck the initial gpul and even the fx only had 512k. I have a feeling the MP is gonna SCREAM even if it **only** clock to 2.5GHz.

Higher clocking might not be so far-fetched. It *is* two cores, and they're implementing PowerTune and independent caches, which hints at (but doesn't dictate) independent clocks and asynchronous glue. *If* they've gone partially async, propagation delays hold a lot less sway over what the clocked sections do. It also makes overall throughput much, much harder to guess at.

[Eugene]

I just hope Apple doesn't give it some silly label like "Shotgun" or "Double Barrel."

I also think the 970MP in no way implies quad G5s.

[gsxrboy]

Will powertune et all be able to throttle down individual cores?

[Morpheus]

Dave, Tom, Frontline! I'm starting to feel at home! Anyone else? Pitty there are no walls here... I guessed right, that some of us would be lurking around these boards...

Morpheus

[Morpheus]

Dave,

Make that 125, 66, 153

Morpheus

[Morpheus]

Originally Posted by gsxrboy Will powertune et all be able to throttle down individual cores?

No

Morpheus

[Morpheus]

Small correction: Pin comp = false, of course...

Morpheus